1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices and, more particularly, the present invention relates to an improved method of manufacturing semiconductor devices which incorporate MOS transistors.
2. Description of the Related Art
Integrated circuits, CMOS transistors and logic gates currently are typically realized in planar silicon technology, with lateral arrangement of a source, channel region and drain. The gate lengths obtainable in such a design are dependent on the resolution of the optical lithography employed and the tolerances in structuring and adjustment thereof. Typical gate lengths of 0.6 .mu.m can be achieved by 16M generation and typical gate lengths of 35 .mu.m can be achieved by 64M generation.
Further miniaturization of the lateral channel lengths is desired in view of the electrical properties of MOS transistors as well as the increased packing density that has become especially desirable in complex logic circuits. In these designs, a plurality of n-channel and p-channel transistors must be both insulated from one another and wired to one another. Improvements in optical lithography as well as in lacquer and etching technology are required in order to accomplish further miniaturization. As a result of the limited resolution of optical lithography and increasing problems with tolerances in the structuring and adjustment of these manufacturing processes, it is doubtful that transistors having channel lengths below 100 nm can be reliably manufactured with these procedures. Moreover, miniaturization of the lateral channel lengths results in modification of the electrical properties of the MOS transistor which must be compensated by implantation of dopants in the channel region as well as by increased design complexity of source/drain structures.
Smaller structural sizes can be achieved in planar technology when optical lithography is replaced by electron beam lithography. Manufacturing individual, functional MOS transistors having channel lengths down to 50 nm has been accomplished with an electron beam printer on a laboratory scale. However, because electron beam lithography is slow, it is economically unsuitable for use in semiconductor fabrication on a large scale.
As an alternative to these manufacturing processes, it was proposed in the 1980's (see, for example, F. E. Holmes et al., Solid State Electronics, 17 (1974) pp. 791 ff) to manufacture vertical transistors in what is referred to as V-MOS technology. The source, channel region and drain of these devices are realized as vertical layer sequences in a substrate. Gate dielectric and gate electrode regions are realized at the surface of a trench that has a V-shaped profile. Transistors having channel lengths shorter than that allowed with the lithography available at that time could thereby be manufactured. This proposal did not achieve significance in logic design and development compared with planar manufacturing methods because only the channel length was small in these transistors resulting in large parasitic capacitances for the overall circuit.
In the development of DRAM memories, Texas Instruments (see, for example, W. F. Richardson et al., IDEM Dig. Tech. paper (1985), pp. 714-717) proposed that transistors and capacitors be vertically integrated in what is referred to as a "trench transistor cell". The transistor proposed in such a design comprises a channel length on the order of approximately 1 .mu.m. However, only the arrangement of the capacitor in the trench subsequently prevailed in memory development.
An overview of the use possibilities of molecular beam epitaxy is provided in the introduction to the dissertation by W. Kiunke, 1992, pp. 2-3. In molecular beam epitaxy, uniform layers having a minimum thickness on the order of one layer of atoms can be manufactured in a controlled fashion. Doping in the range from 10.sup.14 cm.sup.-3 through 10.sup.20 cm.sup.-3 is possible in situ during the epitaxy stage by adding a gas containing dopant. As an applied example, a proposal for a vertical CMOS inverter is discussed. The proposed inverter is realized as a mesa structure on a substrate. The mesa structure comprises an npnpnp layer sequence with vertical sidewalls. All vertical sidewalls of the layers are provided with a gate dielectric and a gate electrode at one side. The gate electrode is insulated from the substrate only by the gate dielectric, so that this structure exhibits large parasitic capacitances.
The present invention improves upon these known prior art semiconductor manufacturing methods and provides a technical advance by providing a method of manufacturing semiconductors which can reliably manufacture smaller MOS transistor structures. The invention is directed to a method for manufacturing MOS transistors having a defined channel length in the range down to below 50 nm. In particular, the method is suitable for the manufacture of compact, high speed logic gates.